The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having an embedded microcomputer with an ECC (Error Checking and Correcting) function.
When data written in a semiconductor memory is erroneously read therefrom due to a software error or a retention failure, the correction of the erroneously read data using an ECC has been conventionally performed. An example of the application of the ECC to a semiconductor memory is disclosed in, e.g., H. Davis et al., “A 70-ns word-wide 1-Mbit ROM with on-chip error-correction circuits,” IEEE J. Solid-State Circuits, vol. 20, pp. 958-963, 1985. As a method for outputting an error detection signal which is activated when read data contains an error, the following prior art technology has been used.
A conventional memory access controller comprises: a memory module for storing data and error detection/correction codes; an error detection/correction circuit for detecting/correcting an error in data read from the memory module; and a mechanism for retaining data corrected by the error detection/correction circuit. When an error is detected in the data read by the error detection/correction circuit during a process in a mode which transfers the read data directly to a processor, the memory access controller notifies the processor of the occurrence of the error and transfers corrected data retained therein to the processor (see, e.g., Japanese Unexamined Patent Publication No. Hei 9 (1997)-134314).
A conventional error detection/correction system comprises: syndrome generating means for generating an error syndrome based on data read from a data memory and on a check bit read from a check bit memory; error detecting means for detecting an error in the data read from the data memory based on the generated syndrome; error correcting means for correcting the error based on the syndrome temporality stored in a syndrome latch and on the data temporarily stored in a data latch; and means for giving an error detection output from the error detecting means as a retrial command signal for the reading of the data (see, e.g., Japanese Examined Patent Publication No. Hei 6 (1994)-70775).
A retry read control method used in a conventional memory device relates to a method for controlling a retry read access which is performed when an error is detected in data read from a main memory controlled by a main memory control unit. During a retry read access, the main memory control unit references an address buffer and issues a retry read access distinguished from a normal retry read access when the corresponding address is present in the address buffer. On recognizing the retry read access different from the normal retry read access, the main memory returns the read data corrected by a data buffer to the main memory control unit without activating a memory (see, e.g., Japanese Unexamined Patent Publication No. Hei 3 (1991)-41537).